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PIN Descriptions time rate of change of current
SR3.3
PROTECTION PRODUCTS
Applications Information (continued)
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
the TVS clamping voltage and the voltage due to the
parasitic inductance (V C(TOT) = V C + L di/dt) . Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit. An ESD induced transient for
example reaches a peak in approximately 1ns. For a
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
(V = 1x10 -9 (30/1x10 -9 )). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
Minimize the path length between the SR3.3 and
the protected line.
Place the SR3.3 near the RJ45 connector to
restrict transient coupling in nearby traces.
Minimize the path length (inductance) between the
RJ45 connector and the SR3.3.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
? 2008 Semtech Corp.
5
www.semtech.com
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